AMD talks in detail about the next Ryzen: 3D V-Cache at Hot Chips 33

During Hot Chip, the conference dedicated to new computer architectures, AMD talked in more detail about the technology 3D V-Cache announced at the last Computex and that we will see on board a review of Ryzen 5000 CPUs in production by the end of this year and, probably, on sale early next.

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For those who do not remember, in this case we speak of “3D chip“, Where a chip with SRAM stacked vertically above the CCD (complex heart). Specifically, AMD presented at Computex a modified Ryzen 9 5900X prototype characterized by the integration of 64 MB additional cache (SRAM) at 7 nanometers on each chiplet, thus bringing the total L3 cache to 192 MB against 64 MB for a “canon” 5900X.

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According to AMD internal data, the Ryzen 9 5900X prototype with 3D V-Cache technology is able to return 15% higher average performance in 1080p games, with peaks of 25%, compared to the classic Ryzen 9 5900X: this is a jump typically associated with a new architecture and / or an improvement in the production process.

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For now, only one layer of SRAM is stacked on the chip, but technically it is possible to stack more layers in order to further increase the capacity. In addition, AMD said after the presentation that the implementation of the technology has no impact on production yields, as well as negligible on temperatures and power consumption – it is also possible to completely disable the cache when not in use. Most importantly, using the additional cache will not require any software changes.

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To merge the chip with the SRAM on top of the compute matrix, AMD used the TSMC’s SoIC process with a direct copper-copper dielectric connection of TSV vertical interconnects (via silicon vias) which connect the two matrices. The technique chosen does not use soldered microbosses to connect the two chips, which facilitates a denser and more efficient connection.

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AMD indicates a 200 times higher interconnect density than traditional 2D packaging solutions, an improvement in density of 15 times compared to 3D microbump implementations and 3 times more energy efficiency thanks to the direct “copper to copper” link between the two chips. In fact, we are talking about a “step”, that is to say the distance between the TSV connections, of 9 microns – value comparable to the future Intel Foveros Direct (2023) and significantly denser than the 50 microns of the current Foveros technology still used by Intel.

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A two-step bonding technique allows TSMC to fuse the two chips together. In the first phase, a hydrophilic dielectric process on a dielectric is used at room temperature, then “annealing” takes place which binds the dielectric connections. The second phase is a direct copper to copper bond which forms the bonds by diffusion in the solid state.

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AMD keeps the SRAM chip centered on the lower layer L3 cache to reduce SRAM’s exposure to core heat of the underlying processor. In addition, through the same process, it places structural silicon on top of the processor cores in order to standardize the height of the chiplet to ensure better cooling.

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According to AMD, the technology behind 3D V-Cache is much better than the 3D microbump techniques because it guarantees 3 times the interconnection efficiency by consuming less than a third of the energy per bit, 15 times higher density and better signaling and power delivery characteristics. Up to 2TB / s bandwidth between the two arrays ensures minimal latency.

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However, we are only at the start of a journey which will lead to increasingly complex and flexible stacking technologies, with the possibility of placing DRAM memory above the CPU, but also CPU above the CPU. It will also be possible to stack kernel on other kernels and the cores above the uncore part of the CPU, as Intel also did with the Lakefield project, to then arrive at an even bigger stew with central elements of the architecture superimposed or circuits distributed among them (slicing circuit).

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Stacking compute units, in particular, will cause significant difficulty in distributing energy to the upper die and removing heat from the lower dies. Of course, all this will also depend on the improvement in terms of consumption, performance, surface area and cost (PPAC – Power, Performance, Area, Cost).