Intel, Moore’s law valid beyond 2025: the innovations that will allow it

There Moore’s Law says that the number of transistors in a microchip doubles approximately every two years and its merits are debated today: the increasingly high costs of setting up more advanced production processes and the reaching of the physical limits of silicon are two problems which play against an assertion which has made its evidence for almost 50 years.

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Being a formulation of one of the founders of informationthe American company made one mantra and in recent years has always declared, contrary to other realities, that the “Law” is more alive than ever. Current CEO Pat Gelsinger recently went so far as to say the law would become “Great“Where does this belief come from? a series of novelties that the company believes has the potential to extend its validity beyond 2025.

At the IEEE International Electron Devices Meeting (IEDM) 2021, Intel showcased some developments it will be interesting packaging, transistors and quantum physics through which it aims to revolutionize information technology as we know it. Paul Fischer, director and senior principal engineer of the Components Research division told us about it.

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Search for components is an Intel Technology Development research group charged with developing breakthrough processes and new packaging solutions to create products and services that can extend Moore’s Law into the future. The division works with Intel’s various business units, anticipating their future needs and collaborating with external groups, from US government research labs to industry consortia, universities and high-tech industry partners.

The work of Search for components has already yielded tremendous results in recent years, such as innovations such as strained silicon, where a layer of silicon is placed on a silicon germanium substrate, but also High-K Metal Gate (HKMG) materials, FinFET, RibbonFET and EMIB transistors and Foveros Direct packaging solutions. Some of these technologies have already been implemented in Intel chips, others will be soon.

There are three directions in which the Santa Clara house moves: multiply by more than 10 the density of interconnection in the packaging by means of so-called “hybrid bonding“, reduce the size of transistors by 30% to 50%. And apply some notions of quantum physics to the world of silicon.

Miniaturize at all costs with hybrid bonding, 3D CMOS and two-dimensional materials

At IEDM 2021, Intel again talked about Foveros Direct and more specifically about hybrid bonding. The term hybrid bonding refers to the connection of the different dies on the package using very small dies copper-copper connections versus so-called bumpsor small copper dots created on the die and spaced up to 10 microns apart to connect the chip to the package.

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To go beyond these 10 microns e multiply by more than 10 the density of interconnections By providing high-bandwidth power to the chips attached to the case, Intel is banking on hybrid bonding. During the conference, Intel explained all the manufacturing changes needed to reach this milestone and the need to establish new industry standards and procedures to enable an ecosystem of chips connected through a hybrid link.

As for transistorsafter EndFET“, Intel announced in recent months RibbonFETthe term behind which lies its implementation of transistors Door all around (GAA) which other realities are also trying to implement into their production roadmaps as soon as possible.

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The first generation of GAA “RibbonFET” transistors, composed of semiconductors NMOS and PMOS side by side, predicted doors on all sides. This technology will allow higher transistor switching speed with the same drive current as multi-fin chips, but in a smaller footprint.

The next step will be to stack NMOS and PMOS on top of each other, create what Intel calls 3D-CMOS. The company aims to achieve a improved miniaturization from 30% to 50%. Intel is working on several methods to stack NMOS and PMOS semiconductors. Intel is also studying i two-dimensional materialsonly a few atoms thick, to create shorter channels and further miniaturize transistors.

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Silicon gets “superpowers”

Not All Transistors Are Created Equal and, depending on the area of ​​the processor in which they operate and the task they perform, one type may be more appropriate than another. At IEDM 2021, the company explained how it intends to integrate “new capabilities” into silicon.

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At the conference, Intel unveiled the world’s first integration of one GaN Power Switches (rooster nitride) with silicon CMOS on 300mm wafer. This type of switch affects the supply voltage of the transistors to operate with higher voltages. According to Intel, this will lead, among other things, to a reduction of components on the motherboard.

Another area of ​​study concerns the low latency read and write capabilities using new ferroelectric materials to shape the next generation of embedded DRAM. In particular, Intel is working on the FeRAM (Ferroelectric Random Access Memory), a type of memory that can be rendered much more compact than SRAM. Future CPUs will have more and more SRAM, so Intel is looking for a way to deliver high capacity in the smallest footprint possible. FRAM also promises to be faster and with latency on the order of 2 nanoseconds, equal to that of L1 cache.

Intel wants to merge quantum physics and silicon

Intel leads research also in completely new fields, which are closely related to quantum physics. For example, Intel has created a logic device called MESO (magnetoelectric spin-orbit) capable of operating at room temperature. MESO could reduce the voltage by 5 times and the power required by 10 to 30 times compared to current CMOS solutions, while simultaneously offering five times the logic operations in the same space as CMOS.

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MESO is based on a multiferroic material composed of bismuth, iron and oxygen (BiFeO3) which is both magnetic and ferroelectric. The advantage is that these two states are connected or coupled, so changing one also affects the other. It is the manipulation of the electric field that changes the magnetic state.

Finally, Intel and IMEC are advancing the search for spintronic materials to fabricate a fully functional spin-couple device, while Intel has identified a pathway to make scalable quantum solutions compatible with CMOS fabrication.