SiFive Performance P650, RISC-V means business: performance improved by 50% in just a few months!

His name is P650 performance the new core SiFive“frontier” reality in the creation of ISA-based processors RISC-V. The new project – which was scheduled to arrive in October – is not only the fastest in the SiFive Performance family but should also be the “Fastest licensed RISC-V kernel on the market“. According to the American company, the P650 will allow the creation of high-performance RISC-V processors for different sectors.

Based on the previous SiFive P550 introduced in June, the new P650 maintains “an efficient pipeline by expanding the instruction issue width (the maximum number of instructions that can be executed in one clock cycle) to deliver an impressive 40% performance increase per clock cycle“, said Dr. Yunsup Lee, co-founder and CTO of SiFive. improves overall performance by 50% over the previous processor“. SiFive estimates that the Performance P650 core is faster than an Arm Cortex-A77 (released in 2019) in several workloads – so not at the level of the latest Arm designs, but RISC-V is making leaps and bounds very quickly. .

The project has a score of 11+ SPECInt2006/GHz ed scalable up to 16 cores, creating clusters with 1 MB or more of L3 cache available for each core. SiFive says it will offer a preview of the architecture to select customers in the first quarter of 2022, then move to general availability in the middle of the same year. “In SiFive we are determined to prove that RISC-V has no limits and the SiFive Performance P650 is the next step in a far-reaching roadmap,” said Rohit Kumar, Senior Vice President of Engineering at SiFive.

sifive p650 core diagramma 03 12 2021

The P650 was intended for chips manufactured in 5 nanometersprocess that will allow you to set up a clocked at 2.7 GHz or higher. Design-wise, the P650 is a 64-bit (RV64GBC) out-of-order core with a 13-stage four-issue pipeline and three threads, while the previous P550 was a “triple issue”. Customers can configure it to have up to 128 KB of instruction and data L1 cache and up to four 256-bit memory ports. Other innovations include the integration of a hypervisor extension that enables paramount hardware virtualization.

In this regard, the organization RISC-V International announced the ratification of 15 new specifications, for more than 40 extensions, of the RISC-V ISA involving scalar and vector cryptography and precisely hypervisors. The new extensions will help “unlock new opportunities for developers building RISC-V applications for artificial intelligence (AI) and machine learning (ML), Internet of Things (IoT), connected and self-driving cars, data centers and more » , the organization said.

Yunsup CEO Lee will talk about future SiFive products and the P650 at the upcoming RISC-V Summit 2021, December 6-8, at the Moscone Center in San Francisco.

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